Joint EIE / SIT seminar

Transactors and RAMP

Associate Professor Krste Asanovic
Massachusetts Institute of Technology

Friday 07 July 2006, 1-2 pm (Please note different day/time)

School of IT Building, Room 123

Abstract

A perfect storm awaits designers of future information processing devices. The boundary between general-purpose and embedded systems has disappeared, as most products now combine the functional complexity of traditional computing environments with the resource constraints of traditional embedded environments. Software development for general-purpose processors can no longer rely on improvements in uniprocessor performance. Hardware development of custom chips has become economically infeasible except for the highest volume parts. The bulk of the effort in future product development will consist of parallel programming of highly-concurrent substrates. Unfortunately, the systems community is far behind in developing an abstraction stack (architectures, operating systems, languages, libraries) to support effective development of such parallel systems.

The RAMP (Research Accelerator for MultiProcessors) project is developing a large-scale multiprocessor emulation platform based on FPGAs, to revolutionize parallel systems research by allowing rapid interaction across the whole systems community. RAMP allows architects to quickly deliver credible prototypes of thousand-processor systems that are fast enough (~100 MHz) to be used by software developers but which can be easily modified based on experience, reducing the typical hardware-software iteration loop from five years to days. In ten months, the RAMP project has snowballed from a hallway discussion at a computer architecture conference into a multi-university collaboration with substantial industry support. In this talk, I will present the technical underpinnings of the RAMP project. RAMP is built on a transactional actor (transactor) model of computation, from which the configuration compiler automatically generates a distributed cycle-accurate event simulator using both hardware and software components.

Speaker's biography

Krste Asanovic is an Associate Professor in the MIT Department of Electrical Engineering and Computer Science, and a member of the MIT Computer Science and Artificial Intelligence Laboratory. He received a B.A. in Electrical and Information Sciences from Cambridge University in 1987 and a Ph.D. in Computer Science from UC Berkeley in 1998. His primary research interests are computer architecture and VLSI design.