FPGA-based Low Latency Trading

Summary

This project involves the development of low-latency trading systems using FPGA hardware.

Supervisor(s)

Associate Professor Philip Leong, Associate Professor Craig Jin, Dr Alistair McEwan

Research Location

Electrical and Information Engineering

Program Type

PHD

Synopsis

A field programmable gate array (FPGA) is an array of logic gates in which the functionality and interconnection can be configured by downloading a bitstream into its memory. They combine the programmability of microprocessors with the speed and flexibility of application specific integrated circuits (ASICs). FPGAs can be used to accelerate problems in areas as diverse as signal processing, networking, scientific computing and financial engineering, this field of research being known as reconfigurable computing.  Low latency is a focus of many trading systems on Wall Street and their systems use traditional PC technology and have latencies measured in milliseconds. In this research, we will develop trading algorithms suited for direct hardware implementation on an FPGA as well as design prototype reconfigurable hardware which combines a network interface controller (NIC) and trading logic on the same device.  This should result in an order of magnitude reduction in latency.

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Keywords

FPGA, reconfigurable computing, financial engineering, networking, computer architecture

Opportunity ID

The opportunity ID for this research opportunity is: 1058

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