Placement-aware Hardware Description Languages

Summary

This project aims to develop hardware description languages for expressing spatially parallel hardware.

Supervisor(s)

Associate Professor Philip Leong, Associate Professor Craig Jin, Dr Alistair McEwan

Research Location

Electrical and Information Engineering

Program Type

PHD

Synopsis

FPGA designs have very fast internal components but achievable clock rates for most designs are modest. In this work, methods for automatically generating highly pipelined designs with spatial locality so clock frequency can be maximised will be studied.  We will begin by developing hand-optimised designs of blocks such as correlators, filters and floating point units and then develop tools which can derive the same design from a high level description.  Ultimately, a high level programming language for FPGA devices in which both placement and computation can be described will be developed.

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Keywords

FPGA, reconfigurable computing, parallelism, hardware description language, behavioural synthesis

Opportunity ID

The opportunity ID for this research opportunity is: 1060

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