FPGA-based low latency machine learning

Summary

This project involves the design of novel low-latency trading systems by combining FPGA hardware and machine learning.

Supervisor(s)

Professor Philip Leong, Associate Professor Craig Jin, Dr Alistair McEwan

Research Location

Electrical and Information Engineering

Program Type

PHD

Synopsis

A field programmable gate array (FPGA) is an array of logic gates in which the functionality and interconnection can be configured by downloading a bitstream into its memory. They combine the programmability of microprocessors with the speed and flexibility of application specific integrated circuits (ASICs). FPGAs can be used to accelerate problems in areas as diverse as signal processing, networking, scientific computing and financial engineering, this field of research being known as reconfigurable computing. In this research, we have two aims: (1) develop new machine learning algorithms which are amenable to FPGA implementation and which are optimised for latency, and (2) develop real-time systems which can integrate such ML systems with a network interface controller (NIC) on the same FPGA in order to improve performance. Systems designed in this fashion should result in at least an order of magnitude reduction in latency. Applications of this work include trading systems (low latency is a focus on Wall Street), machine prognostics and real-time ML systems.

Additional Information

Web link for Computer Engineering Lab: http://www.ee.usyd.edu.au/cel/index.html

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Keywords

FPGA, reconfigurable computing, Machine learning

Opportunity ID

The opportunity ID for this research opportunity is: 2040

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