Real-time Low-power Neural Accelerator

Summary

This project aims at developing an Application-Specific Integrated Circuit (ASIC) for a low-power learning system processing real-time time-series data.

Supervisor(s)

Dr Omid Kavehei

Research Location

Electrical and Information Engineering

Program Type

PHD

Synopsis

For over a decade, the semiconductor industry, that propelled us all into the digital age, has been struggling with a chip power-density crisis. The birth of multi-cores microprocessors has its root in this very challenging issue of fundamental physics. The known thermal-voltage (kT/q) parameter, which identifies the scalability of basic transistor parameters, is a non-scalable factor. Additionally, the minimum feature size of the transistors has continuously shrunk from 10μm in 1970 to just 14nm in 2015 (iPhone 6S was shipped with 14nm transistors) making it extremely difficult and costly to engineer energy barriers in transistor channels (where electrons move) to avoid excessive electron tunneling through the barrier when the transistor is supposed to be OFF. Success of the industry has traditionally been measured by how effectively they avoid quantum mechanical effects, such as the tunneling. Unfortunately, with a few tens of atoms across a sub-10nm transistor switch, such effectiveness is vanishing into the shadow of ever increasing quantum tunneling. This project aims to develop a neuro-inspired computing platform for cognitive task that current supercomputers fail to do in real-time like human brain [1-3]. The system architecture is inspired by how the brain function and solely dedicated to tasks dealing with big-data, including data mining, data analytics, pattern recognition and feature extraction.We use our state-of-the-art GPU cluster to develop the software and integrated circuit design tools to explore hardware implementation.
References:
[1] Kavehei, Omid, and Efstratios Skafidas. "Highly scalable neuromorphic hardware with 1-bit stochastic nano-synapses." 2014 IEEE International Symposium on Circuits and Systems (ISCAS).
[2] Kornijcuk, Vladimir, et al. "Multiprotocol-induced plasticity in artificial synapses." Nanoscale 6.24 (2014): 15151-15160.
[3] Kavehei, Omid, Efstratios Skafidas, and Kamran Eshraghian. "Memristive in situ computing." Memristor Networks. Springer International Publishing, 2014. 413-428.

Want to find out more?

Contact us to find out what’s involved in applying for a PhD. Domestic students and International students

Contact Research Expert to find out more about participating in this opportunity.

Browse for other opportunities within the Electrical and Information Engineering .

Keywords

microelectronics, Neuromorphic Engineering, www.deepnano.ai

Opportunity ID

The opportunity ID for this research opportunity is: 2391

Other opportunities with Dr Omid Kavehei